1. Field of the Invention
The present invention relates to a semiconductor device and a method of its fabrication, and more particularly, to a memory device having a highly integrated cell structure and a method of its fabrication.
2. Description of Related Art
Nonvolatile memory devices do not lose their stored data even if their power is interrupted. In general, nonvolatile memory devices employ flash memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode, which are sequentially stacked on a channel. Accordingly, the tunnel oxide layer should have improved film quality and the coupling ratio of the flash memory cells should be increased to enhance the reliability and programming efficiency of the flash memory cells.
Novel nonvolatile memory devices, for example, phase-change memory devices, have been proposed as a substitute to conventional flash memory devices. In the phase-change memory devices, a unit cell includes a cell switching device and a phase-change material layer connected to the cell switching device. In this case, an upper electrode and a lower electrode are provided on and under the phase-change material layer, respectively. The lower electrode may be electrically connected to the cell switching device, and the upper electrode may be electrically connected to a bit line provided on the phase-change material layer. The cell switching device may be an active device, such as a MOS transistor.
Particularly in recent years, semiconductor devices are highly integrated. Accordingly, to enhance the integration density of a memory device, it is necessary to reduce the area occupied by a unit cell of the memory device.
A large program current, which is supplied through the MOS transistor, of at least several mA is required to program the phase-change memory cell. To reduce the area occupied by the unit cell of the memory device, the area of the MOS transistor used as the switching device needs to be reduced. However, it is technically difficult to reduce its area.
Also, the phase-change material layer should be formed to a small size to scale down the unit cell of the memory device. In particular, when the phase-change material layer is formed in an island form using typical photolithography and etching processes, there is a technical limit in reducing its size.
Furthermore, as the integration density of the memory devices increases, since the area of the unit cells of the memory device correspondingly decreases, it may be difficult to form the upper electrode contacting a top surface of the phase-change material layer. In particular, as the size of the phase-change material layer decreases, the margin of the process of forming the upper electrode interposed between the phase-change material layer and the bit line provided on the phase-change material layer also decreases, and thus the process of forming the upper electrode becomes difficult. Specifically, the upper electrode, which is interposed between the phase-change material layer and the bit line and in contact with the top surface of the phase-change material layer, may include a top electrode contact (TEC) and a contact plug. In forming the TEC, which contacts the top surface of the phase-change material layer, and the contact plug, which connects the TEC and the bit line, the phase-change material layer may be misaligned with the contact plug as a consequence of the downscaling of the phase-change material layer. Thus, the phase-change material layer may be misaligned with the bit line.
Therefore, it is necessary to develop a novel structure and method for reducing the area occupied by the unit cells of the memory device to increase the integration density of the memory device.